Chiplets Run Hot and Nobody Can Model Why

The semiconductor industry is shifting from monolithic chips to heterogeneous chiplet architectures — assembling multiple small dies from different process nodes and materials into a single package through advanced packaging (2.5D interposers, 3D stacking, fan-out wafer-level packaging). This approach circumvents the end of Moore's Law scaling but creates a thermal management crisis: stacking chips multiplies power density, while the interfaces between chiplets, interposers, and thermal solutions introduce thermal resistance barriers that don't exist in monolithic designs. No integrated thermal analysis framework spans the full scale hierarchy — from nanometer-scale hotspots within transistors, through micrometer-scale die-level heat spreading, to millimeter-scale package conduction, to centimeter-scale system cooling. Chip designers, package engineers, and system thermal engineers use separate tools with incompatible models, discovering thermal problems only after physical prototypes are built.

Data center electricity consumption is projected to reach 4-8% of US electricity by 2030, with cooling accounting for 30-40% of that energy. AI training accelerators (GPUs, TPUs) now exceed 700W per package and are heading toward 1000W+, generating heat flux densities rivaling rocket nozzles in localized hotspots. The CHIPS and Science Act has invested $52+ billion in domestic semiconductor manufacturing, but without thermal co-design tools, advanced chiplet systems designed in the US may be performance-limited by thermal constraints that weren't visible during the design phase. Thermal failures are already the leading cause of semiconductor reliability issues, and heterogeneous integration worsens every contributing factor.

Finite element thermal simulation at chip level (Ansys Icepak, Cadence Celsius) captures transistor-level hotspot details but requires days of compute time for a single design point and can't practically model package and system interactions. Package-level thermal models (3D compact thermal models, Delphi models) abstract away chip-level details, losing the hotspot information that drives reliability. System-level CFD (Fluent, FloTHERM) models airflow and heat sink performance but treats the chip as a uniform heat source. Attempts to couple these tools require manual transfer of boundary conditions between incompatible meshes, formats, and assumptions, introducing errors and preventing iteration. Multi-physics simulation platforms exist but are prohibitively slow for the iterative co-design loop that heterogeneous integration requires. Thermal test vehicles (TTV) provide empirical validation but arrive too late in the design cycle to influence architecture decisions.

A hierarchical thermal modeling framework that enables rapid co-simulation across scales — propagating chip-level hotspot maps up to package and system models and feeding cooling constraints back down to chip placement and power budgeting decisions — in minutes rather than days. This likely requires physics-informed reduced-order models or neural network surrogates trained on high-fidelity simulations. Standard thermal interface characterization methods for chiplet-to-interposer and interposer-to-substrate bonding layers would also close a critical data gap, as these interfaces account for up to 50% of total thermal resistance but their properties vary widely with bonding process conditions.

A student team could develop a reduced-order thermal model of a 2.5D chiplet package using proper orthogonal decomposition (POD) trained on a set of COMSOL finite element simulations, validating accuracy and speedup against full simulations. Alternatively, a team could design and execute a thermal characterization study of different die-attach and thermal interface materials using a thermal test chip with embedded diode temperature sensors, generating interface resistance data that is currently sparse in the literature. Relevant disciplines include electrical engineering, mechanical engineering (heat transfer), materials science, and computational methods.