digital · manufacturing · energy · family: the answer is in a field you’ve never heard of
chipletsrunhotandnobodycanmodelwhy
Heterogeneous chiplet integration lacks multiscale thermal design tools
Problem statement
The semiconductor industry is adopting heterogeneous integration — assembling many semiconductor components from different manufacturing processes in a common platform through advanced packaging, with components interconnected in a horizontal plane (2D and 2.5D) or stacked vertically (3D). NSF's FuSe2 solicitation gives, among its examples of research under its heterogeneous integration topic, the thermal side of this: thermal management techniques for high power and high power densities, especially in 3D configurations and specifically for cooling the chips at the bottom of a stack; cooling solutions for hot-spot management; and low-thermal-resistance interface materials. Among its examples of heterogeneous integration design tools are thermal analysis design tools that integrate across scales from the chip level to the server level and apply to heterogeneous integration, and a system-technology co-optimization framework for the design and validation of chiplet systems. The solicitation describes current practice as independent research and discovery in each area (materials, devices, systems) separately, with advances often not effectively translated to practice.
Why this matters
FuSe2 names the need to reduce the energy consumption of computation and communication technologies as a technological driver, and says continued advances in capabilities and reductions in costs across computing, sensing, and communications are threatened. The ASCENT solicitation says the industry is experiencing exponential demand for communication bandwidth and compute performance scaling, fueled by rapid growth of mobile devices and AI/ML, and calls heterogeneous integration important to the modern-day economy and crucial for national security. FuSe2 says co-design projects in heterogeneous integration should include advanced and integrated thermal management solutions for component reliability.
What’s been tried and why it hasn’t worked
Neither solicitation reviews existing thermal simulation tools or says why they fall short. What FuSe2 does say is that developments in materials, processes, devices, and architectures have often progressed independent of the application area, which has delayed their incorporation into next-generation technologies, and that current practice focuses on independent research and discovery in each area separately. It asks proposers on the heterogeneous integration topic to describe the current state of the art and the specific challenges their research will address, and to include plans to validate or demonstrate their co-designs relevant to current and advanced industry technologies.
What would unlock progress
Thermal analysis design tools that integrate across scales from the chip level to the server level and apply to heterogeneous integration — the item FuSe2 lists — together with a system-technology co-optimization framework for the design and validation of chiplet systems. FuSe2 also lists low-thermal-resistance interface materials development and integration, novel embedded cooling solutions, and thermal isolation of high-power-density components among its examples. ASCENT's FY25 example topics include efficient die/package co-design and thermal solutions for wafer-scale and panel-scale systems.
Entry points for student teams
A student team could develop a reduced-order thermal model of a 2.5D chiplet package using proper orthogonal decomposition (POD) trained on a set of COMSOL finite element simulations, validating accuracy and speedup against full simulations. Alternatively, a team could design and execute a thermal characterization study of different die-attach and thermal interface materials using a thermal test chip with embedded diode temperature sensors, generating interface resistance data. Relevant disciplines include electrical engineering, mechanical engineering (heat transfer), materials science, and computational methods.
Genes
Structural cousins: stuck the same way, in other fields
Sources
NSF 24-521: Future of Semiconductors (FuSe2), Program Solicitation; accessed 2026-02-15; NSF 25-503: Addressing Systems Challenges through Engineering Teams (ASCENT), Program Solicitation; go to source 1 ↗ go to source 2 ↗
Working notes
Notes made while writing and checking this brief, shown as written. They use working shorthand.
The NSF FuSe2 solicitation (NSF 24-521) lists among its examples for its heterogeneous integration topic "Thermal analysis design tools that integrate across scales from chip-level to the server-level, and applicable to heterogeneous integration" and a "System-technology co-optimization framework for ease of design and validation of chiplet systems and for effective use of foundry offerings." ASCENT (NSF 25-503) says that in FY25 it "will focus on wafer-scale or panel-scale heterogeneous integration of innovative semiconductor systems through advanced packaging." Related problem: semiconductor-panel-scale-integration.md addresses the manufacturing side of advanced packaging; this brief addresses the thermal design tool gap that prevents effective thermal co-design.
Reconciliation 2026-10-01: Fact repair after reading the whole write-up against the two sources it names. Both are NSF program solicitations, fetched on 2026-10-01 directly from nsf.gov and read in full: NSF 24-521, Future of Semiconductors (FuSe2), posted December 18, 2023 (https://www.nsf.gov/funding/opportunities/fuse2-future-semiconductors/506141/nsf24-521/solicitation), and NSF 25-503, ASCENT, posted October 9, 2024 (https://www.nsf.gov/funding/opportunities/ascent-addressing-systems-challenges-through-engineering-teams/505853/nsf25-503/solicitation). These are funding calls. They list research areas; they do not report measurements, name commercial software, or review earlier work, so most of the body could not stand on them and was replaced with what they say. Nothing was re-sourced from elsewhere. (1) Source line: it called FuSe2 an "NSF ECCS" program of the Division of Electrical, Communications and Cyber Systems. The solicitation is issued by several NSF directorates and divisions together with industry partners; that division is one of them. The line now gives the solicitation's own title, and adds the title and link for ASCENT, which was named without either. (2) Problem Statement: the text said stacking "multiplies power density," that "no integrated thermal analysis framework spans the full scale hierarchy" from nanometer hotspots to centimeter system cooling, and that chip, package and system engineers use incompatible tools and find thermal problems only after prototypes are built. None of this is in the solicitations, and neither are fan-out wafer-level packaging, interposers, or "the end of Moore's Law." FuSe2 lists as examples of research under its heterogeneous integration topic (it says the examples "do not indicate they are of any special interest to the NSF") thermal management for high power densities especially in 3D configurations, cooling the chips at the bottom of the stack, hot-spot cooling, low-thermal-resistance interface materials, and thermal analysis design tools that integrate across scales from chip level to server level; it says current practice is independent research in each area separately. The section now says that, with the description of heterogeneous integration taken from ASCENT. (3) Why This Matters: removed because neither source contains them: data centers at 4-8% of US electricity by 2030 with cooling at 30-40% of it; AI accelerators above 700W heading to 1000W+; heat flux "rivaling rocket nozzles"; the CHIPS and Science Act and its $52+ billion; and thermal failures as "the leading cause of semiconductor reliability issues." The section now gives the solicitations' own reasons: energy consumption of computing as a driver, exponential demand for compute, economic and national-security importance, and thermal management for component reliability. (4) What's Been Tried: the whole account of existing tools (Ansys Icepak, Cadence Celsius, Delphi compact models, Fluent, FloTHERM, thermal test vehicles, "days of compute time," manual transfer of boundary conditions) is not in either solicitation. The section now says so plainly and reports what FuSe2 does say about fields advancing independently. (5) What Would Unlock Progress: removed "in minutes rather than days," the sentence that this "likely requires" reduced-order models or neural network surrogates, and the claim that bonding interfaces "account for up to 50% of total thermal resistance"; none is in the sources. The section now lists the tools and example research areas the solicitations name. (6) Entry points: removed the statement that interface resistance data is "currently sparse in the literature," which the sources do not make; both starting points are kept. (7) Source Notes: the second quotation attributed to FuSe2, "system-technology co-optimization frameworks for chiplet systems," was not the solicitation's wording; it now carries the solicitation's sentence. The two quotations attributed to IBM Fellow Vijay Narayanan appear in neither solicitation and no other source is named for them, so the sentence was taken out. Confirmed in the sources and left as written: the FuSe2 quotation on thermal analysis design tools (the solicitation capitalises "Thermal") and the ASCENT quotation on its FY25 focus. Not changed: the two titles, which carry no number; "lacks" and "nobody can model why" are stronger than the solicitation, which lists such tools as a research area without saying none exist. Genome tags untouched. A second reader went over these repairs on the same day against both solicitations, fetched again from nsf.gov and read in full; every repair stood, and four phrases were softened so the write-up calls the solicitations' lists what they are, examples of possible research rather than tools asked for or stated research areas (Problem Statement, What's Been Tried, What Would Unlock, Source Notes), and "against" became "relevant to" in the validation sentence, which is the solicitation's word.