Every Qubit Slightly Different

Current fabrication processes for quantum devices cannot achieve the precision, defect control, or reproducibility needed for scalable quantum information systems. Three critical gaps converge: (1) no process can place point defects in diamond (nitrogen-vacancy centers) at specific locations with nanometer precision for quantum networking; (2) superconducting and dielectric thin films for transmon qubits cannot be deposited with sufficiently low defect densities to avoid decoherence at millikelvin temperatures; (3) no 3D integration process exists for combining quantum and classical electronic components on a single chip. NSF DCL 22-074 identifies quantum manufacturing as requiring fabrication precision 1–2 orders of magnitude beyond current semiconductor manufacturing capabilities.

The quantum computing market is projected at $65–125 billion by 2030. The CHIPS and Science Act allocated $200 million specifically for quantum manufacturing research. IBM, Google, and other companies have roadmaps to million-qubit systems by the 2030s, but these roadmaps assume fabrication capabilities that don't exist. Current superconducting quantum processors (IBM Eagle, Google Sycamore) have qubit-to-qubit variability of 10–30% in coherence times — unacceptable for error-corrected computation, which requires uniform, reproducible qubits. Without a manufacturing breakthrough, quantum computing will remain at the "demonstration" stage indefinitely.

Ion implantation for NV center creation in diamond achieves ~35% conversion efficiency and ~50 nm spatial resolution — but quantum networking requires near-unity conversion at <10 nm precision, 5× and 5× beyond current capability respectively. MBE and sputtering of superconducting films (niobium, aluminum) produce material with two-level-system (TLS) defects at interfaces that limit coherence — the defect physics is not well understood, making systematic improvement difficult. Flip-chip bonding for 3D integration (connecting quantum and classical chips) introduces parasitic modes and thermal management challenges at millikelvin temperatures. Each fabrication challenge has been studied individually, but the integrated problem — making millions of identical quantum devices with classical control electronics on a single platform — remains untouched.

Understanding and controlling the atomic-scale defect physics of superconductor-insulator interfaces (the dominant source of qubit decoherence). Developing diamond growth or post-processing techniques for deterministic NV center placement. Creating cryogenic-compatible 3D integration processes — potentially adapting advanced semiconductor packaging (chiplets, through-silicon vias) for millikelvin operation. Rapid in-line characterization tools that can measure quantum-relevant properties (coherence time, defect density) at fabrication speed rather than requiring days-long cryogenic testing.

A student team could study how thin-film deposition parameters (substrate temperature, pressure, deposition rate) affect TLS defect density in aluminum oxide tunnel barriers, using room-temperature microwave loss measurements as a proxy for cryogenic performance. Alternatively, a team could design and simulate a 3D integration scheme for quantum-classical coupling, evaluating electromagnetic crosstalk and thermal management using finite-element modeling. Relevant skills: thin-film deposition, materials characterization, cryogenics, electromagnetic simulation, semiconductor process engineering.