manufacturing · digital · materials · family: it worked in the lab
features toosmall to measure
Semiconductor metrology cannot measure what it needs to control at sub-2nm process nodes
Problem statement
Semiconductor manufacturing at sub-2nm process nodes (gate-all-around FETs, CFET, 3D stacked architectures) requires measuring and controlling features at the atomic scale — individual atomic layer thicknesses, dopant distributions of a few atoms per nm³, and overlay alignment within ±0.3nm. Current metrology tools (CD-SEM, scatterometry/OCD, TEM cross-sections) are approaching fundamental physical limits: CD-SEM cannot resolve features below ~1nm without destructive charging artifacts; scatterometry models become underdetermined as device geometries grow more complex (3D multi-layer stacks); and TEM sample preparation itself alters the structures being measured. The industry faces a measurement crisis where the precision required for process control exceeds the precision achievable by available techniques.
Why this matters
The semiconductor industry generates ~$600B in annual revenue and underpins global technology infrastructure. Moore's Law continuation depends on manufacturing transistors with features measured in atoms, and manufacturing yield depends on metrology — you can't control what you can't measure. At the 2nm node (in production by 2025–2026) and beyond, fab yield losses from undetected process variation could make advanced nodes uneconomical. TSMC, Samsung, and Intel each invest >$1B annually in metrology R&D. The metrology gap is one of three consensus show-stoppers for sub-1nm nodes, alongside EUV stochastic defects and thermal management.
What’s been tried and why it hasn’t worked
Hybrid metrology (combining multiple techniques with model-based analysis) extends current tools but requires increasingly complex models with more floating parameters than the data can constrain. EUV-based scatterometry provides better resolution than DUV but adds cost and complexity. Atom probe tomography (APT) offers atomic-resolution 3D composition mapping but is destructive, slow (hours per sample), and has limited field of view (~100nm). X-ray metrology (SAXS, CD-SAXS) provides non-destructive subsurface measurement but measurement speed is limited by X-ray source brightness — most demonstrations on logic devices have used synchrotron facilities, which are obviously not fab-compatible. Machine learning on metrology data can improve precision for known process variations but can't detect novel defect modes that weren't in the training set.
What would unlock progress
Compact, high-brightness X-ray sources (inverse Compton scattering, compact synchrotrons, advanced X-ray tubes) could bring synchrotron-quality measurements to the fab floor. Alternatively, in-situ process sensing — measuring critical parameters during deposition, etch, and lithography rather than after — would shift from inspection-based to real-time control, potentially leapfrogging the resolution limits of post-process metrology. Novel probe concepts (quantum sensing with NV centers, terahertz near-field microscopy) are in early research but face their own scaling challenges.
Entry points for student teams
A team could analyze the measurement uncertainty budgets for a specific metrology technique (e.g., OCD scatterometry on a gate-all-around structure) and quantify how uncertainty scales with device complexity (number of layers, geometric parameters). This would identify which measurements will fail first as architectures evolve. Alternatively, a team could prototype a simple in-situ sensor concept (e.g., real-time film thickness via ellipsometry or reflectometry during ALD deposition) and test whether closed-loop control improves process uniformity. Skills: physics, optics, signal processing, semiconductor process engineering.
Genes
Tags marked “under review” were questioned by a later calibration pass; they stay visible here but are left out of filters until re-adjudicated.
Structural cousins: stuck the same way, in other fields
Sources
IRDS (International Roadmap for Devices and Systems), "Metrology" chapter, IEEE, 2022; SEMI Technology Symposium proceedings; Orji et al., "Metrology for the next generation of semiconductor devices," Nature Electronics 1, 532–547 (2018), go to source ↗
Working notes
Notes made while writing and checking this brief, shown as written. They use working shorthand.
The temporal:worsening tag reflects the relentless node shrinkage that outpaces metrology capability. The lab-to-field-gap captures the synchrotron-to-fab translation challenge. Distinct from existing semiconductor briefs: manufacturing-pfas-free-semiconductor-processes (chemical constraints), semiconductor-chiplet-thermal-codesign (thermal management), MANUFACTURING-semiconductor-panel-scale-integration (packaging scale-up). Cross-references: materials-nist-reference-material-certification-bottleneck (measurement standards), construction-concrete-compressive-strength-real-time-gap (in-process measurement), chemistry-pharma-crystallization-polymorph-control (process control at molecular scale).
Reconciliation 2026-09-29: A site review read the whole write-up against two of its three sources. Orji et al. 2018 was read in full on 2026-09-29, including Table 1 and the figure captions, from the PubMed Central author manuscript PMC6605074, fetched from https://eutils.ncbi.nlm.nih.gov/entrez/eutils/efetch.fcgi?db=pmc&id=6605074. Its citation was checked against https://api.crossref.org/works/10.1038/s41928-018-0150-9. The IRDS 2022 Metrology chapter (66 pages) was downloaded on the same day from https://irds.ieee.org/images/files/pdf/2022/2022IRDS_MET.pdf. It was searched by keyword and the matching passages were read; it was not read line by line. Its Table MET-3, which holds the lithography and overlay requirements, is not included in the PDF. The third source, "SEMI Technology Symposium proceedings," gives no title, year or address and could not be found. (1) The text said that for X-ray metrology "spatial resolution is limited by X-ray source brightness" and that "synchrotron facilities achieve the required resolution." Both sources say that brightness limits how fast a measurement can be made. Orji et al. say the brightness of compact X-ray sources "leads to long measurement times," and their Table 1 lists "Compact X-ray sources limit throughput." The IRDS chapter says in-line use needs better compact sources "to get the required throughput," and that most reported demonstrations for logic applications used large synchrotron facilities. The sentence now says that. Confirmed and left as written: the Source line for Orji et al. (Nature Electronics, volume 1, pages 532–547, 2018) and for the IRDS chapter (2022 edition, copyright IEEE); the "2nm" node with 2025 as its year of production, and gate-all-around, CFET and 3D stacked devices as the structures that follow (IRDS Table MET-2); scatterometry fitting as an inverse problem without a unique solution, which gets harder as structures get more complex; TEM as destructive, with sample preparation that can produce artifacts; hybrid metrology as a way to extend current instruments; atom probe tomography as needing a milled tip and analysing a volume of about 80 nm by 80 nm by 200 nm; inverse Compton scattering sources as one possible route to brighter compact X-ray sources; in situ measurement as a route to real-time control. The two sources differ on one point. Orji et al. say current instrument limits are "mostly driven by engineering issues, rather than the underlying physics." The IRDS chapter says fundamental physical limits also affect the resolution and sensitivity of metrology. The phrase "approaching fundamental physical limits" follows the IRDS chapter and was left. NOT found in either source that was read, and left as written because the third source could not be opened: the ~$600B annual revenue figure; that TSMC, Samsung and Intel each invest more than $1B a year in metrology R&D; that the metrology gap is "one of three consensus show-stoppers" alongside EUV stochastic defects and thermal management; that yield losses could make advanced nodes uneconomical; overlay within ±0.3nm (in Orji et al. the 0.3 nm figure is a requirement for nanowire roughness and uniformity, and the IRDS overlay table could not be read); dopant distributions of a few atoms per nm³; that CD-SEM cannot resolve features below ~1nm without charging artifacts; that hybrid models have more floating parameters than the data can constrain; that EUV scatterometry gives better resolution than DUV at added cost; "hours per sample" for atom probe tomography; that machine learning cannot detect defect modes missing from its training set; compact synchrotrons and advanced X-ray tubes; and quantum sensing with NV centers and terahertz near-field microscopy. Genes untouched.