manufacturing · digital · energy · family: making one is easy. making a million is the problem
ai needs more bandwidththan packages can deliver
The I/O performance wall — semiconductor packaging cannot scale to meet AI compute demand
Problem statement
AI model growth is driving exponential demand for compute, but performance is not scaling in step with it because of memory bandwidth, I/O bandwidth, and power barriers; Intel frames the goal as increasing compute integration, through wafer- or panel-scale heterogeneous integration, to get past industry-wide I/O performance walls. The industry needs to move from individual chip packages to wafer-scale (300mm) or panel-scale (500mm x 500mm) heterogeneous integration — stitching together compute, memory, photonics, power delivery, and cooling onto a single massive substrate — but thermal solutions, system power delivery, communication fabrics that reach from panel edge to panel edge without active repeaters, and improved manufacturing, reliability, and yield are among the research areas the solicitation and Intel's page list at this scale.
Why this matters
The NSF solicitation calls heterogeneous integration important to the modern economy and crucial to national security, with potential applications including communications and sensing, high-performance computing, biotech and healthcare, power and energy, transportation, and aerospace. Performance is not scaling with compute demand because of memory and I/O bandwidth and power barriers, and packaging performance benefits from shorter interconnections and finer pitches. Panel-scale integration on panels such as glass provides more than 3x the area of wafer-scale integration, but in these sources it exists as a concept illustration and a research agenda rather than a demonstrated system. Intel puts the I/O energy cost of moving data around large data-center networks at as much as two orders of magnitude above moving it within a compute package; NSF frames heterogeneous integration as a matter of economic importance and national security.
What’s been tried and why it hasn’t worked
Packaging performance benefits from shortened interconnection and finer pitches. Components interconnected in a horizontal plane (2D and 2.5D) can also be stacked vertically (3D) for significantly improved performance, and industry is adopting this integration approach in next-generation systems. Test strategies for improved yield and methods for system resiliency are among the potential research areas Intel lists at panel scale. Electromagnetic compatibility and electromagnetic interference in heterogeneously integrated systems are named as an example topic in the solicitation. The power delivery plane and optical communication plane at panel scale appear as a concept illustration on Intel's page and as research areas in the solicitation (system power delivery; optical backplanes and switches; fabrics that reach from panel edge to panel edge without active repeaters). The solicitation says a new semiconductor co-design approach is necessary at the sub-system and system levels.
What would unlock progress
New thermal management architectures for dense heterogeneous integration; co-design methodologies that optimize compute, memory, I/O, and power delivery as a unified system rather than separate components; panel substrates such as glass (Intel's example) and other material alternatives; optical couplers and backplanes; and optical and electrical communication fabrics that reach from panel edge to panel edge without active repeaters, alongside ultra-low-energy I/O. The solicitation requires teams whose topic spans at least two of NSF's three ECCS clusters (Communications, Circuits, and Sensing-Systems; Electronics, Photonics and Magnetic Devices; Energy, Power, Control, and Networks), highly encourages proposals spanning all three, and says teams may include expertise beyond them.
Entry points for student teams
A student team could design and simulate a thermal management solution for a multi-chiplet module, comparing substrate materials (silicon, organic, glass) under realistic power density profiles using finite element analysis. This is feasible with standard simulation tools (COMSOL, ANSYS) and provides publishable results. Alternatively, a team could prototype and characterize signal integrity through a heterogeneous interposer using PCB test structures that mimic panel-scale interconnect geometries at accessible dimensions.
Genes
Structural cousins: stuck the same way, in other fields
Sources
"ASCENT: Addressing Systems Challenges through Engineering Teams," NSF-Intel Partnership, Solicitation NSF 25-503. (accessed 2026-02-10). go to source ↗
Working notes
Notes made while writing and checking this brief, shown as written. They use working shorthand.
- NSF ASCENT is a partnership with Intel specifically targeting heterogeneous integration challenges.
- Intel has published on panel-scale integration as a research priority: https://www.intel.com/content/www/us/en/research/panel-scale.html
- Cross-domain connection: the thermal management challenge shares structure with problems in concentrated solar power and high-power laser systems where thermal dissipation at density is also a binding constraint.
- Neither source mentions the chiplet standardization effort (UCIe — Universal Chiplet Interconnect Express); it is noted here only as a related industry effort, not as a finding of these sources.
- Related problem: electromagnetic compatibility at heterogeneous integration densities could be a separate brief.
Reconciliation 2026-09-30: Fact repair after reading the whole write-up against both sources it names; a second reader went over the repairs against the same sources on the same day and tightened the wording of four of them. The NSF solicitation NSF 25-503 was fetched on 2026-09-30 directly from https://www.nsf.gov/funding/opportunities/ascent-addressing-systems-challenges-through-engineering-teams/505853/nsf25-503/solicitation and read in full by both readers (posted October 9, 2024; the FY25 program description, "ASCENT 2025: Wafer-Scale or Panel-Scale Heterogeneous Integration of Innovative Semiconductor Systems through Advanced Packaging," is the passage that matters; the second reader also read the PDF of the solicitation at nsf-gov-resources.nsf.gov/files/nsf25503.pdf, which carries the same passage). Intel's panel-scale research page refuses scripted requests (403), so it was read in full from the Internet Archive capture of 2026-07-10 (web.archive.org/web/20260710100200/www.intel.com/content/www/us/en/research/panel-scale.html); the link in the note above is left as it is. (1) The problem statement said conventional packaging "creates memory bandwidth, I/O, and power delivery bottlenecks between chips." Intel's page says performance is not scaling in tandem with AI compute demand "due to memory and I/O bandwidth and power barriers" and that the aim is to increase compute integration, using wafer- or panel-scale heterogeneous integration, to overcome industry-wide I/O performance walls; the sentence now says that. (2) The problem statement said the "fundamental physics" of thermal management, signal integrity, power delivery and manufacturability "are unsolved." Neither source says this, and signal integrity is not named; the solicitation and Intel's page list thermal solutions, system power delivery, edge-to-edge communication fabrics without active repeaters, improved manufacturing and reliability, and test strategies for improved yield as research areas, and the sentence now lists those as research areas. (3) "Semiconductors underpin every critical technology sector" and "defense" are not in the sources; the paragraph now gives the solicitation's own framing (important to the modern economy, crucial for national security) and its list of potential applications. The sentence that faster transistors no longer make faster systems "because the interconnects between chips are the bottleneck" is not in the sources; it now gives Intel's barriers and the solicitation's statement that performance benefits from shortened interconnection and finer pitches. (4) "Roughly 3x" the area is now "more than 3x," which is Intel's figure, and the qualifier "panels such as glass" is Intel's. "No one has demonstrated it" is not in the sources; the text now says the panel-scale system exists in these sources as a concept illustration and research agenda. "Binding constraint," "direct U.S. national security and economic competitiveness concern" and "concentrated global semiconductor supply chains" are not in the sources; the sentence now gives Intel's two-orders-of-magnitude comparison of data-movement energy cost between data-center networks and a compute package, and the solicitation's economic and national-security framing. (5) The "What's Been Tried" section was rewritten to what the sources say, because most of it was not in them: 2D packaging "fundamentally limited"; silicon interposers; 3D stacking creating "thermal hotspots that degrade reliability"; AMD and Intel chiplet products "limited to small substrates" (AMD appears in neither source); warpage and thermal stress multiplying "dramatically"; EMI "poorly understood"; "no one has demonstrated" a power delivery or optical plane; and co-design lacking "adequate tools and methodologies." The section now gives the solicitation's statements on interconnection and pitch, 2D/2.5D/3D integration and its industry adoption, yield and resiliency as potential research areas on Intel's page, EMC/EMI as an example topic in the solicitation, the planes as Intel's concept illustration and the solicitation's research areas, and the solicitation's sentence that a new co-design approach is necessary. (6) In "What Would Unlock Progress," glass with "better thermal and electrical properties than organic laminates" is not in the sources (Intel names glass as an example panel; the solicitation says cost reduction involves material alternatives); photonics that "replace electrical I/O" is not in the sources, which list optical couplers and backplanes, and optical and electrical fabrics with edge-to-edge reach and ultra-low energy I/O, as research areas; and the three named disciplines are not in the sources, which require at least two of the three ECCS clusters, highly encourage proposals spanning all three, and say teams may include expertise beyond them. Each now follows the source. (7) The Source Note on UCIe is not from either source and now says so. Confirmed in the sources and left as written: the title's "I/O performance wall" (Intel's phrase is "I/O performance walls"); exponential compute demand driven by AI model growth; wafer scale up to 300 mm and panel scale 500 mm x 500 mm (the solicitation says "or larger"); compute, memory, photonics/optical I/O, power delivery and cooling as the planes of the concept system; Intel as funding partner of the FY25 ASCENT program; and the Source line's solicitation number. Not checked because they are the write-up's own suggestions rather than sourced claims: the two student entry points, the named simulation tools, and the cross-domain note on solar and laser thermal management. No title changed. Genome tags untouched.